Firmware based Bug Finding Mechanisms in Pre-Silicon Environment

Ankit Chandankhede *

Senior Member of Technical Staff, Advanced Micro Devices, Inc, Texas, USA
 
Review
International Journal of Science and Research Archive, 2020, 01(01), 133-140.
Article DOI: 10.30574/ijsra.2020.1.1.0030
Publication history: 
Received on 10 October 2020; revised on 23 November 2020; accepted on 26 November 2020
 
Abstract: 
In continuous progression of Moore’s Law, modern architectures in CPU , GPU and custom chips have introduced different features based on the modern application of datacenters, gaming consoles and edge computing. This has significantly increased the complexity of design space and exponentially increased the verification space. With increasing competition, it is pivotal to reduce the verification cycles as well as meet the bug finding techniques tap-out milestone. Quality of the verification can be easily achieved with the bug finding techniques proposed in this paper. These techniques not only facilitate to finding bugs at early stage of design but also provide the quality metric to sign off the closing milestones. Further proposed method provides the evaluation and confidence in health of design based on the market centric workloads.
 
Keywords: 
Firmware; Bug Finding Mechanisms; Pre-Silicon Environment; Bug finding techniques; Bug finding techniques
 
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Copyright © 2020 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution Liscense 4.0