Acceleration of test sequences for graphics architecture testing at subsystem and SoC Level

Ankit Chandankhede *

Senior Member of Technical Staff, Advanced Micro Device Inc., USA.
 
Review
International Journal of Science and Research Archive, 2020, 01(01), 155-164.
Article DOI: 10.30574/ijsra.2020.1.1.0023
Publication history: 
Received on 28 September 2020; revised on 23 December 2020; accepted on 26 December 2020
 
Abstract: 
Graphics Processing Units are known for parallel computing and rendering process and have complex architecture.  Compute and rendering process involves complex functions and shaders which introduces challenges in design as well as verification through the design development cycle. Test suite used for verifying such complex design runs longer and hence consumes magnitudes of turnaround time to run a test, retest any bug fixes, as well as running regression. Most of these test suites uses similar configuration and initialization of the design which often contributes to 30-40% of test simulation cycles which usually are stable after certain stage of design.  This paper proposes methodology to save the state of design after the configuration and initialization phase which can be restored before the run phase for different workloads, thus allows to start the testcase from rendering or compute workload. This improves the efficiency of simulation test as the proposed method skips through the initialization and configuration cycles and saves about 30-40% simulation time at Multsubsytem and SOC.
 
Keywords: 
Graphics Processing Unit (GPU); Simulation Time; Functional Simulation Database (FSDB); Pre-Silicon Verification; Universal Verification Methodology (UVM)
 
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Copyright © 2020 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution Liscense 4.0